Recent advances in the miniaturization of integrated circuits have led to smaller chip areas available for devices. High density dynamic random access memory chips (DRAMs), for example, leave little room for the storage node of a memory cell. Yet, the storage node (capacitor) must be able to store a certain minimum charge, determined by design and operational parameters, to ensure reliable operation of the memory cell. It is thus increasingly important that capacitors achieve a high stored charge per unit of chip area occupied.
Traditionally, capacitors integrated into memory cells have been patterned after the parallel plate capacitor. A layer of dielectric is deposited between the deposition of two conductive layers and the layers are patterned, either sequentially during deposition or all at once. The patterned dielectric becomes a capacitor dielectric while the patterned conductive layers become the top and bottom plates or electrodes of the resultant capacitor structure. The amount of charge stored on the capacitor is proportional to the capacitance, C=.epsilon..epsilon..sub.0 A/d, where .epsilon. is the dielectric constant of the capacitor dielectric, .epsilon..sub.0 is the vacuum permittivity, A is the electrode area and d is the spacing between electrodes.
Several techniques have recently been developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area occupied by the cell. These include increasing the effective surface area of the electrodes by creating folding structures, such as trench or stacked capacitors. Such structures better utilize the available chip area by creating three dimensional shapes to which the conductive electrodes and capacitor dielectric conform. The surface area of the electrodes may be further increased by providing a roughened surface to the bottom electrode, over which the capacitor dielectric and the top electrode are conformally deposited. Other techniques concentrate on the use of new dielectric materials having higher dielectric constants (.epsilon.).
As DRAM density has increased and memory cells packed more closely together, the three dimensional folding structures designed to increase the electrode surface area have become complicated and expensive to fabricate. Thus, greater attention is now being given to the development of thin film dielectric materials, including ferro-electrics which yield very high capacitance relative to conventional dielectrics. Such materials effectively possess dielectric constants significantly greater than convention dielectrics (e.g., silicon oxides and nitrides). Whereas .epsilon.=3.9 for silicon dioxide, the dielectric constants of these new materials are generally greater than 300, and some even higher (600-800). Using such materials allows the creation of much smaller and simpler capacitor structures for a given stored charge requirement.
Among the high-.epsilon. or ferro-electric materials being studied, much attention has been paid to barium strontium titanate (BST), lead zirconate titanate (PZT), and strontium bismuth tantalate (SBT). However, technical difficulties have been encountered in incorporating these materials into current integrated circuits with conventional fabrication techniques. The problems with these materials have thus far prevented their use in large scale, commercial production of integrated circuits such as DRAMs or SRAMs.
For example, chemical vapor deposition (CVD) of PZT and BST is often accompanied by oxidation of polycrystalline silicon (polysilicon) electrodes. Therefore, the electrodes should advantageously comprise a noble metal, such as platinum. Nevertheless, oxygen may diffuse through the platinum bottom electrode to oxidize any silicon underlying the bottom electrode (e.g., a polysilicon plug or the silicon substrate). Although diffusion barriers may be incorporated to protect any underlying silicon from oxidation, these diffusion barriers are costly to integrate into the manufacturing process flow and are at any rate subject to breakdown during subsequent processing.
Use of ferro-electric materials introduces other special requirements for the process flows. One of the advantages of ferro-electric materials is the sharp switching characteristics of memory cells incorporating them, allowing their use in non-volatile memory applications. These switching characteristics, however, are sensitive to any variation in the thickness of the ferro-electric layer. Thus, the fabrication process should be such as to produce a ferro-electric layer of substantially uniform thickness for the capacitor dielectric.
Deposition of a high-.epsilon. or ferro-electric layer over a pre-patterned bottom electrode may also lead to structural defects in the resultant capacitor. In order to produce a high capacitance value, dielectric layers in general should be as thin as possible without risking short circuits, since the thickness of the dielectric layer represents the spacing between electrodes, or d in the denominator of the capacitance formula set forth above, and this is thought to be true of ferro-electric layers as well. At any rate, a thin layer will generally conform to the surface of a pre-patterned bottom electrode, including the vertical sidewalls of the bottom electrode. Curving over the bottom electrode corners may not raise problems for conventional, amorphous dielectrics such as oxides. Many high-.epsilon. dielectrics and ferro-electrics, however, are crystallized prior to patterning, and mechanical stresses at the corners of the bottom electrode tend to cause cracking in the dielectric layer during or after the crystallization process.
Furthermore, these new dielectric materials demonstrate chemical and physical instability under a variety of conditions common in current integrated circuit processing. For example, high temperature processes and plasma processes are known to degrade certain high-.epsilon. and ferro-electric materials. Very few techniques are therefore available for etching these materials without breaking down the dielectric layer and causing shorts.
Thus, a need exists for a process flow for fabricating a capacitor having a high-.epsilon. dielectric layer of substantially uniform thickness. Such a process flow should avoid chemical or physical breakdown of the dielectric material, or short circuiting across the capacitor electrodes.